As integration level of integrated circuits (ICs) increases and supply voltage decreases, dimensions of semiconductor devices of the ICs shrinks. This requires more improvement in chip manufacturing processes. The performance of semiconductor devices is significantly affected by improvements in chip manufacturing processes. Reliability tests for semiconductor devices are often conducted to evaluate the performance of the semiconductor devices.
Threshold voltage of MOS transistors is an important factor indicating reliability of memories. Currently, wafer acceptance test (WAT) is usually used to obtain the threshold voltage of a MOS transistor in a storage array of static random access memory (SRAM). The basic principle of WAT is to measure test keys on the scribe lines of a wafer to obtain the performance parameters of individual semiconductor devices.
As shown in FIG. 1, a wafer 11 is divided into a plurality of chips 13 by scribe lines 12. Individual semiconductor devices, which are used as test keys, can be formed on the scribe lines 12 when making the chips 13. Referring to FIG. 2, test keys M20 and M21 are located on the scribe lines 12. By measuring the test keys M20 and M21, properties of MOS transistors around the scribe line 12 can be obtained.
When measuring threshold voltage of a PMOS transistor in a SRAM storage array, corresponding DC voltages are applied to bonding pads connected to drain/source of the test key M20 and the substrate. A sweep voltage is applied to a bonding pad connected to the gate of the test key M20. While applying such sweep voltage, a drain current in the test key M20 is measured. A characteristic curve of the measured drain current in the test key M20 versus the gate voltage (i.e., a difference in potential between the gate and the source) can be obtained, and the threshold voltage of the test key M20 can then be calculated according to the characteristic curve.
The threshold voltage of the test key M20 represents the threshold voltage of the PMOS transistor in the SRAM storage array. Similarly, the threshold voltage of an NMOS transistor in the SRAM storage array can also be measured by measuring the threshold voltage of the test key M21.
Accurate assessment of SRAM reliability necessitates a statistic analysis by obtaining threshold voltages of a large number of MOS transistors in the storage array. However, when using WAT to obtain the threshold voltages of the MOS transistors, each test key must be connected to four bonding pads, including bonding pads of the gate, drain, source, and the substrate. Consequently, use of WAT cannot obtain threshold voltages of a desirably large number of MOS transistors in the SRAM array due to limited space of the scribe line 12 for arranging test keys and bonding pads.